FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5749 Discussions

ArriaV thansceiver jitter tolerance

danduan
Beginner
205 Views

Hi, my FPGA chip is 5AGXBA3D4F31C4,  i want to ask some help for transceiver jitter tolerance.

1. For Receiver PHY,  PMA  includes CDR module,  i want to know the CDR module jitter tolerance value, or the requirement for the incoming serial data jitter. 

2. For Transceiver IP, is there some parameters to configure for CDR pll bandwidth?  or if FPGA datasheet or userguide to be refered in the intel webset?

0 Kudos
5 Replies
CheePin_C_Intel
Employee
203 Views

Hi danduan,


As I understand it, you have some inquiries related to the CDR jitter tolerance in the AV devices. Please see my responses as following:


1. For Receiver PHY, PMA includes CDR module, i want to know the CDR

module jitter tolerance value, or the requirement for the incoming

serial data jitter.

[CP] For your information, there is no generic jitter tolerance specs available in the datasheet. The AV CDR is characterized to be compliant to the jitter tolerance requirement of the supported protocols. Therefore, you can refer to the requirement in the supported protocol specs ie Ethernet. You can refer to the device handbook -> "Transceiver Protocol Configurations in Arria V

Devices" section on the supported protocols.


2. For Transceiver IP, is there some parameters to configure for CDR pll

bandwidth? or if FPGA datasheet or userguide to be refered in the intel

webset?

[CP] You can use the "CDR_BANDWIDTH_PRESET" QSF assignment to configure the bandwidth. You can refer to "Analog Settings Having Global or Computed Values for Arria V Devices" section in the XCVR PHY user guide.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin


danduan
Beginner
200 Views

Hi Chee Pin,

Thanks for your answer. I have another question.

 1. I am trying to modify the parameter "CDR_bandwidth_preset", if i configure it to high,  does it improve the CDR jitter tolerance?  what is the difference between high and low ? For CDR pll, increasing CDR bandwidth,  whether the pll will better trace the incoming data.

 2. another parameter is PPM detector threshold, Its description is the maximum PPM difference the CDR can

tolerate between the input reference clock and the recovered clock. If I configure it to 1000,  it means the recovered clock will be worse ???      

 

danduan
Beginner
193 Views

Hi Chee Pin,

Thanks for your answer. I have another question.

 1. I am trying to modify the parameter "CDR_bandwidth_preset", if i configure it to high,  does it improve the CDR jitter tolerance?  what is the difference between high and low ? For CDR pll, increasing CDR bandwidth,  whether the pll will better trace the incoming data.

 2. another parameter is PPM detector threshold, Its description is the maximum PPM difference the CDR can

tolerate between the input reference clock and the recovered clock. If I configure it to 1000,  it means the recovered clock will be worse ???      

CheePin_C_Intel
Employee
188 Views

Hi,


Sorry for the delay. Please see my update to your latest inquiries:


1. I am trying to modify the parameter "CDR_bandwidth_preset", if i configure it to high, does it improve the CDR jitter tolerance? what is the difference between high and low ? For CDR pll, increasing CDR bandwidth, whether the pll will better trace the incoming data.

[CP] For your information, the following are the discrepany between high vs low bandwidth setting. A high-bandwidth PLL/CDR provides a fast lock time and tracks jitter on the reference clock source, passing it through. A low-bandwidth PLL/CDR filters out reference clock jitter, but increases lock time.


Generally if you encounter jitter tolerance issue in your system, it is recommended for you to try with different bandwidth setting to see which one will helps.


2. another parameter is PPM detector threshold, Its description is the maximum PPM difference the CDR can tolerate between the input reference clock and the recovered clock. If I configure it to 1000, it means the recovered clock will be worse ???

[CP] For your information, value = 1000 meaning the maximum ppm difference between refclk and recovered clock that CDR can tolerate is +/-1000ppm. This is the maximum value that a CDR tolerate. It does not affect the recovered clock.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin


CheePin_C_Intel
Employee
182 Views

Hi,


Just would like to follow up with you on this. Thank you.


Reply