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mifa
Beginner
395 Views

Avalaon MM BFM read problem

Hi,

I am trying to read from my custom IP, but i have the problem that the BFM Master does not see any kind of acknowledge by the slave.

 

My IP combines multiple interfaces with an Avalon Pipeline bridge to a single slave interface. The internal interfaces are very standard like SGDMA descriptor and CSR, APB translator.

 

Firstly, I wondered why my slave IP triggered no readdatavalid. But that seems to be normal for that subinterfaces. Therefore, I deactivated the "readdatavalid" port at the BFM.

 

But now there is some automatism I dont understand that an interconnect is placed between BFM and IP, which modifies the bus signals. As result, the slave shows a dip at "waitrequest" but on BFM side there is no more dip. At the end the BFM does not know when the transaction is finished and throws a timeout error.

 

How do I handle the BFM correctly?

 

Current setup:

altera_avalon_mm_master_bfm #( .AV_ADDRESS_W (32), .AV_SYMBOL_W (8), .AV_NUMSYMBOLS (4), .AV_BURSTCOUNT_W (1), .AV_READRESPONSE_W (8), .AV_WRITERESPONSE_W (8), .USE_READ (1), .USE_WRITE (1), .USE_ADDRESS (1), .USE_BYTE_ENABLE (1), .USE_BURSTCOUNT (0), .USE_READ_DATA (1), .USE_READ_DATA_VALID (0), .USE_WRITE_DATA (1), .USE_BEGIN_TRANSFER (0), .USE_BEGIN_BURST_TRANSFER (0), .USE_WAIT_REQUEST (1), .USE_TRANSACTIONID (0), .USE_WRITERESPONSE (0), .USE_READRESPONSE (0), .USE_CLKEN (0), .AV_CONSTANT_BURST_BEHAVIOR (1), .AV_BURST_LINEWRAP (1), .AV_BURST_BNDR_ONLY (1), .AV_MAX_PENDING_READS (0), .AV_MAX_PENDING_WRITES (0), .AV_FIX_READ_LATENCY (1), .AV_READ_WAIT_TIME (1), .AV_WRITE_WAIT_TIME (0), .REGISTER_WAITREQUEST (0), .AV_REGISTERINCOMINGSIGNALS (0), .VHDL_ID (0) )

 Regards

 

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5 Replies
mifa
Beginner
87 Views

It works if I manually instantiate the BFM in the top-level file and not in the QSYS with the IP. This will prevent that QSYS inserts an interconnect between them which does more bad than good.

Anyways, I would like understand the problem because it would be more confortable to use the BFM in qsys.

 

There must be a wrong or missing information anywhere, which causes the interconnect to build something wrong between the BFM and the custom IP. Any suggestions? Is there a parameter which tells the pipeline bridge to work without readdatavalid?

sstrell
Honored Contributor II
87 Views

Without seeing the design, it's hard to tell what's going on. I'd recommend creating a Platform Designer testbench system. Create a new .qsys file that includes just your custom component, and export all its interfaces. Then choose to create a testbench system from the Generate menu. This will automatically create a system with the master BFM (and clock and reset BFMs) set up appropriately and connected to your IP. See this online training for details:

 

https://www.intel.com/content/www/us/en/programmable/support/training/course/oaqsyssim.html

 

#iwork4intel

mifa
Beginner
87 Views

Thank you for the course link I will try to take a look on it.

 

Meanwhile, I got a better "workaround". The BFM returned to the testbench system. If I add an onchip memory to my testbench system then the tool is forced to implement another interconnect which connects my IP and the memory with the BFM. This will generate readdatavalid signals from the IP.

 

Of course, the configuration of the BFM has to be adjusted.

altera_avalon_mm_master_bfm #( .AV_ADDRESS_W (32), .AV_SYMBOL_W (8), .AV_NUMSYMBOLS (4), .AV_BURSTCOUNT_W (1), .AV_READRESPONSE_W (8), .AV_WRITERESPONSE_W (8), .USE_READ (1), .USE_WRITE (1), .USE_ADDRESS (1), .USE_BYTE_ENABLE (1), .USE_BURSTCOUNT (1), .USE_READ_DATA (1), .USE_READ_DATA_VALID (1), .USE_WRITE_DATA (1), .USE_BEGIN_TRANSFER (0), .USE_BEGIN_BURST_TRANSFER (0), .USE_WAIT_REQUEST (1), .USE_TRANSACTIONID (0), .USE_WRITERESPONSE (0), .USE_READRESPONSE (0), .USE_CLKEN (0), .AV_CONSTANT_BURST_BEHAVIOR (1), .AV_BURST_LINEWRAP (0), .AV_BURST_BNDR_ONLY (0), .AV_MAX_PENDING_READS (4), .AV_MAX_PENDING_WRITES (0), .AV_FIX_READ_LATENCY (1), .AV_READ_WAIT_TIME (1), .AV_WRITE_WAIT_TIME (0), .REGISTER_WAITREQUEST (0), .AV_REGISTERINCOMINGSIGNALS (0), .VHDL_ID (0) )

 

KennyT_Intel
Moderator
87 Views

can u attached your design in *zip files so that I can take a look?

KennyT_Intel
Moderator
87 Views

any update?

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