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Novice
141 Views

Avalon Dual-Master Bus with constant waitrequest on connection point

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I want to connect a DDR4-Ram-Controller to 2 different master controller:

 

                                                                                                         DDR4

                                                                                                               |

                                                                                                               |

PCI-E <---> Avalon-mm-bridge (pcie-pipe) <---> Avalon-mm-bridge (mem-pipe) <---> Avalon-mm-bridge (sys-pipe) <---> Custom-Logic

 

 

If I connect either PCI-E or my custom logic, everything works fine. However as soon as I connect both I see a constant wait request in pcie-pipe and sys pipe, but not in mem pipe. Due to the constant wait request my design end up in a dead-lock situation.

 

This actually also happens with other memory like dual-port-memory. Has anyone an idea why this happens? I will upload an minimal example later. For now I attach my custom Avalon-mm-master maybe I messed this on up?

 

Or could it be related to the different clock domains? (I already tested a design using clock-cross, but the result didn’t change, I guess Qsys adds a clock crosser anyway.)

 

All bridges are pipelined, I set the “Maximum pending read transactions” 32, like in an example I saw, should I change this option with multiple masters?

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Employee
58 Views

That's correct. Your master can initiate a transaction to a slave when wait request is asserted.

Actually wait request asserted is the default condition also if no transaction is on going in most of slave IP and interconnect.

When your master start the transaction you put on the bus address/cmd/data and must keep all stable until the wait request signal is deasserted. cmd = read or write

This is all reported in the Avalon specification.

If you look into the  "Typical Read and Write Transfers" chapter here you can immediately read it in the note:

"waitrequest can be decoupled from the read and write request signals. waitrequest may be asserted during idle cycles. An Avalon® -MM master may initiate a transaction when waitrequest is asserted and wait for that signal to be deasserted. Decoupling waitrequest from read and write requests may improve system timing. Decoupling eliminates a combinational loop including the readwrite, and waitrequest signals"

This explains what you see and your logic shall cope with that.

 

Hope it helps

 

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3 Replies
Highlighted
67 Views

Hi Sir,

 

Can you re-send the attachment so that I can take a closer look? I am not able to view it as it is corrupted.

 

Regards,

Aida

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Highlighted
Novice
62 Views

Sorry for taking so long to reply, hopefully it's not to late.

Attached is an example of a dual avalon master setup, now using a cyc5 + on chip memory instead of the stratix 10. But it behaves the same.

When using 2 masters on the slave the slave will continously out put waitrequest high, but after asserting read/write on one master the signal will goes low during the transfer.

So the transfer works, I just wonder is this waitrequest=high in idle normal for multimaster setups?

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Highlighted
Employee
59 Views

That's correct. Your master can initiate a transaction to a slave when wait request is asserted.

Actually wait request asserted is the default condition also if no transaction is on going in most of slave IP and interconnect.

When your master start the transaction you put on the bus address/cmd/data and must keep all stable until the wait request signal is deasserted. cmd = read or write

This is all reported in the Avalon specification.

If you look into the  "Typical Read and Write Transfers" chapter here you can immediately read it in the note:

"waitrequest can be decoupled from the read and write request signals. waitrequest may be asserted during idle cycles. An Avalon® -MM master may initiate a transaction when waitrequest is asserted and wait for that signal to be deasserted. Decoupling waitrequest from read and write requests may improve system timing. Decoupling eliminates a combinational loop including the readwrite, and waitrequest signals"

This explains what you see and your logic shall cope with that.

 

Hope it helps

 

View solution in original post