FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5990 Discussions

Avalon FIFO stuck in reset

Altera_Forum
Honored Contributor II
853 Views

Hello everyone, 

 

I am having an issue where one of my FIFOs in the qsys system is stuck in reset. I have a simple loopback system, where data comes into the first FIFO from the HPS, passes from the first to the second through the FPGA (the output of the first FIFO and input of the second is exported from qsys), then exits back out through the HPS. I have tapped all the avalon_mm ports in SignalTap to observe the system behaviour. The first FIFO is behaving as expected, while all lines of the second FIFO are zero or low (I'm assuming) because its reset line is active.  

 

The resets for both FIFOs are tied to the reset bridge in qsys, and are shared according to the RTL netlist viewer. However, only one FIFO is stuck in reset. I'm not sure if its the code I'm runnng on the ARM causing one FIFO to reset and the other to run (The resets appear to be tied for both FIFOs so both should have the same reset state). Maybe it is because I exported the input of the FIFO from qsys to the top level and it breaks the link to the reset? I know I saw a warning in qsys about exporting the reset to match the exported input, but I ignored it since I'd have to export the entire reset bridge, and the fact that the message goes away if the untie and tie the warning line back up in qsys. 

 

Does anyone else have any idea what the cause could be, or how I can test/correct the issue? Feel free to ask if you need further clarification on anything. 

 

Thanks, 

Bogg
0 Kudos
0 Replies
Reply