i'm trying to use the Avalon -MM Intel Stratix 10 Hard IP+ for PCI Express for my FPGA application but the use guide doesn't provide me enough informations for my level of knowledge. Is there any other document that i can start with? Thanks.
Yes, if without using the DMA, you can disable the Read/Write mover, and use the Busting Avalon MM interface for host to communicate with your application layer.
Thank you for your reply.
Now i gotta decide if i need both the master and slave bursting interfaces or i can just stick to one of them.
In my design i have a RX and a TX module. (rx and tx name depends on the communication with a camera , not the pcie).
The first one reads a memory location and sends the data over the pcie to the host computer.
The second one receives a data from host through the pcie and writes it in a memory location (another memory, not the previous one).
DO you think i need to use both the interfaces slave and master or i can just use one of them since they are bidirectional?
I forgot to say that in the RX module, i send the data to the host everytime the memory is not empty. So if there is data in memory, a process will fetch it from the memory and sends it to the host.
In the TX part, if the memory is not full, a process will allow the reception of data from the host at the memory location specified by the TX module (not specified by the host).
I tried to generate the example design but i get this error:
Info: avmm_bridge_512_0: Auto-generation of QSYS example design beginning...
Info: avmm_bridge_512_0: Validating example design parameters and selection...
Info: avmm_bridge_512_0: Parametrization is valid.
Info: avmm_bridge_512_0: Auto-generation of QSYS example design in progress based on variant parameter settings
Info: avmm_bridge_512_0: Pin assignments are not included in pcie_ed.qsf
as no development kit is specified.
Info: avmm_bridge_512_0: save_system C:/Users/Admin/AppData/Local/Temp/alt8353_40724721456274277.dir/0002_avmm_bridge_512_0_gen/pcie_ed.qsys
Info: avmm_bridge_512_0: Generating QSYS system pcie_ed.qsys
Info: avmm_bridge_512_0: Running: qsys-script --pro --script=pcie_ed.tcl
Error: avmm_bridge_512_0: Unable to create pcie_ed.qsys, read pcie_ed_tcl_log.txt for log
Info: avmm_bridge_512_0: Copied pcie_ed.tcl and pcie_ed_tcl_log.txt to the example design directory.
Error: Failed to generate example design example_design to: C:\Designes\TRUEVIEW\pcie_hard_ip\avmm_bridge_512_0_example_design
Also if i open the file pcie_ed_tcl_log.txt i read:
2020.03.31.17:24:14 Warning: Both --quartus-project and --new-quartus-project switches are not used. A new Quartus project named pcie_ed will be created using the tcl script filename: C:\Users\Admin\AppData\Local\Temp\alt8352_8205035805552475495.dir\0051_avmm_bridge_512_0_gen\pcie_ed...
2020.03.31.17:24:14 Info: Doing: qsys-script --pro --script=C:/Users/Admin/AppData/Local/Temp/alt8352_8205035805552475495.dir/0051_avmm_bridge_512_0_gen/pcie_ed.tcl
2020.03.31.17:24:28 Error: Failed to create Quartus Project, manually re-run the commands included in C:\Users\Admin\AppData\Local\Temp\alt8352_8205035805552475495.dir\0051_avmm_bridge_512_0_gen\quartus... in Quartus tcl shell.
Any advice, please?
The bursting slave interface allows the user application in the FGPA to access the PCIe system memory. Do you use FPGA (endpoint) to issue a memory read/write request to the host? If yes, then you need this interface.
As for the example design generation, I use v19,3 to generate the example design, and it works well. Could you please try to use v19.3 if you are not doing so?