FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5988 Discussions

Avalon-MM PCIe Hard IP problem in 64bits address range

Altera_Forum
Honored Contributor II
804 Views

I'm using a Avalon-MM Hard IP for PCIe with a modular Scatter-Gather DMA (mSGDMA) on a Cyclone V. The FPGA PCIe is connected to a Window 10 CPU board. The Windows 10 driver I wrote is reading and writing and reading registers through the PCIe BAR0 and it's working well. I'm using the BAR0 to write descriptor in the mSGDMA and I see the mSGDMA sending read request to the PCIe TXS port. The read address is the one I'm sending from the Windows driver but the request is never answer (see attachment for signaltap waveform). After a few request que Txs_waitrequest signal stay high and 

the Txs_readdatavalid is always low. The Txs_address width is 64bits 

 

 

I've done some test and I've found that when I read data in the address range 0 to 0xFFFFFFFF (32 bits) I receive answer to request but when I enter the 64bits address range it fail. I'm not sure if the problem is in the PCIe Hard IP or in Windows. 

 

 

How can I receive timeout flags of failing requests from the Transaction Layer Errors? I read the "Cyclone V Avalon-MM Interface for PCIe Solutions User Guide" but I don't understand how Transaction Layer Errors works. 

 

I'm using quartus 15.1.2 and the cores version is 15.1
0 Kudos
0 Replies
Reply