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Honored Contributor I

Avalon-MM PCIe connecting two FPGAs not working



I try to connect two Cyclone V SoCs by a highspeed transceiver using the Avalon-MM PCIe core. 

One FPGA is configured as root the other as endpoint. The PCIe link between both FPGAs is up (ltssmstate keeps in L0). 

If I try to do a read transaction on the Txs Interface of the root the Avalon bus stalls. As fare as I can see the bus master flag is not set an therefore the state machine is not generating the PCIe packets (no tx_st_* signals are changing). 

How can I set the bus master flag? 

Do I have a wrong understanding for using this cores?
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