Avalon MM slave component: readdata signal is always zero

[MateusSoares]

I have this simple Avalon MM slave component where I set avs_s0_readdata to a constant value:

But avs_s0_readdata always stays with value zero. I've tried to achieve this in three different ways, showed in the code commented. Look at this signal tap logic analizer:

readdata is always 0h, even when read signal is enabled. Shouldn't readdata be always the constant value I set in the component's code? 

[RichardTanSY_Intel]

Do you see the same behavior when you try to simulate the design?

Btw, may I know which Quartus edition and version are you using?

Which device are you using?

Best Regards,

Richard Tan

[sstrell]

Your clk is not toggling according to Signal Tap, so a better question may be how the writes are working!

[RichardTanSY_Intel]

Any update on this?

Regards,

Richard Tan

[RichardTanSY_Intel]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you.

Best Regards,

Richard Tan

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