I am currently using the Triple-Speed Ethernet IP and have read in order to properly use it I need to first configure the register space. In order to do that, believe I need to use the MAC Control Interface Signals here.
I have my code implemented similarly to that included in the testbench but am seeing the signal "reg_busy" stay a 1. The IP User Guide states the reg_busy signal is "asserted during register read / write access and deasserted when the current access completes." However, my simulation never sees the read / write signals go high.
My reg_busy signal is only mentioned a few times:
1. As a wire declaration: "wire reg_busy;"
2. In the QSYS instantiation ".eth_tse_0_control_port_waitrequest (reg_busy),"
3. For some comparisons to proceed in my state machine, and to give values to reg_busy_reg (both of these examples are the same as in the TSE testbench).
I've attached a picture of my simulation.
Thanks in advance for helping.
Your understanding is correct that user needs to configure TSE MAC and PHY register first to initialize the IP core before you can use it.
Regarding reg_busy :
Regarding why reg_busy never deasserted low :
Hi DeshiL and thanks for your response.
I am still unsure why reg_busy is still a ‘0’ despite red_rd and reg_wr also ‘0’. I know the reg config hasn’t completed because my reg_config_done signal is still a ‘0’.
I worry whole TSE IP is still stuck. That could explained why it can't function properly.
I am not even sure whether it's out from reset properly or not.
You may want to checkout following first