Avalon-MM slave shows constant high reg_busy signal (TSE IP).

[GDagi1]

Hi all,

I am currently using the Triple-Speed Ethernet IP and have read in order to properly use it I need to first configure the register space. In order to do that, believe I need to use the MAC Control Interface Signals here.

I have my code implemented similarly to that included in the testbench but am seeing the signal "reg_busy" stay a 1. The IP User Guide states the reg_busy signal is "asserted during register read / write access and deasserted when the current access completes." However, my simulation never sees the read / write signals go high.

My reg_busy signal is only mentioned a few times:

1. As a wire declaration: "wire reg_busy;"

2. In the QSYS instantiation ".eth_tse_0_control_port_waitrequest     (reg_busy),"

3. For some comparisons to proceed in my state machine, and to give values to reg_busy_reg (both of these examples are the same as in the TSE testbench).

I've attached a picture of my simulation.

Thanks in advance for helping.

[Deshi_Intel]

HI,

Your understanding is correct that user needs to configure TSE MAC and PHY register first to initialize the IP core before you can use it.

Regarding reg_busy :

• This is output status signal from TSE MAC to user logic. You shouldn't assign any value to it as it's output status signal, not input signal.
• I am sorry for the confusion in the TSE user guide doc but what it means is - it's an indicator to tell user whether TSE MAC is busy processing something or not. When it's asserted, user shouldn't send further command to TSE MAC anymore. user command should only to sent when reg_busy is low indicating TSE MAC is ready to accept user command now.

Regarding why reg_busy never deasserted low :

• It's hard to tell what's wrong by looking at partial of your sim waveform
• I am not sure which FPGA product that you used but you can always checkout TSE example design to study the expected signal behaviour
• https://fpgacloud.intel.com/devstore/platform/?acds_version=any&ip_core=Ethernet
  • Filter by FPGA product family then by Ethernet IP
• https://www.intel.com/content/www/us/en/programmable/products/intellectual-property/ip/interface-pro...
  • Doc -> reference design link

Thanks.

Regards,

dlim

[GDagi1]

Hi DeshiL and thanks for your response.

I am still unsure why reg_busy is still a ‘0’ despite red_rd and reg_wr also ‘0’. I know the reg config hasn’t completed because my reg_config_done signal is still a ‘0’.

[Deshi_Intel]

HI,

I worry whole TSE IP is still stuck. That could explained why it can't function properly.

I am not even sure whether it's out from reset properly or not.

You may want to checkout following first

• Use the example design to run one time sim to get an idea of expected signal behaviour
• then back to your own design, check the TSE clocking, reset and also your reg_config_done. Let the sim run longer to see if there is any difference. You can also compare the sim run time with working example design as reference.

Thanks.

Regards,

dlim

[Deshi_Intel]

HI,

I am closing this case as well as per my feedback in another forum case while we moved all debug discussion into Andy's case.

Thanks.

Regards,

dlim

[MRigh4]

Hello, I have the same problem, could you post the link where the discussion continued?

Thank you,

Marco