Hello,I'm using one of the Hard Memory Controllers on a 5CGXFC5C6F27C7 from the Terasic Cyclone V GX Starter Kit. The board has a single LPDDR2 chip. I've instantiated the IP, and can get it working perfectly well as long as I don't try to burst reads larger than 4 transfers together (see screenshot). If I set burstcount to 8 or higher, the core seems to accept the read command (waitrequest_n goes low and then high again), but never returns any data (see screenshot, readdatavalid stays low indefinitely). I've set AVL_MAX_SIZE to 128 in the MegaWizard, which should result in a maximum burst size of 128. I've included the top level of the generated IP that shows the parameters I've used. Any clues as to why larger bursts seem to be getting rejected? I must be doing something wrong, but I've run out of ideas. The requests appear to match the Avalon-MM burst timing diagrams shown in the spec: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf I see the same behavior under Quartus 16.1.2 and 17.0.
Just wanted to provide a quick update. After making my controller more configurable I was able to test more thoroughly. It appears burst sizes 1-7 work as expected. Bursts of 8 and higher are broken. The LPDDR2 RAM being utilized has configurable 4/8/16 native burst lengths. It's currently set to 8, which should make an Avalon-MM burst of 8 the most optimal length, but for some reason it doesn't work.
Hi.I seem to have the same problem. I'm using Quartus 16.1.2. and DDR3 SDRAM Controller with UniPHY with Hard Controller. When modeling or seeing SignalTap II Logic Analyzer, I see that the burst larger than 48 does not reading too. Also I see pulsing avl_ready. But workaround didn't help me. https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08142013_467.html Unfortunately I could not view your screenshots, they are too small. Have you solved the problem?