Avalon Master/ Slave Template Third Party Questasim Simulation

[CBOLL2]

Hi,

I have created a project with platform designer, making use of the avalon memory mapped master and slave template IP:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-memory-slave.html

I have written state machines to trigger write and read operations and have tested the design successfully in hardware (Arria 10 GX Development Kit). I am now trying to simulate the same design using 3rd party simulation (questasim). I have compiled the libraries using "EDA Simulation Library Compiler" and created an additional 'do' file to compile my state machines and testbench. The simulation will run however, the writedata is never presented at the slave's writedata output port after a write command. Looking at the wave window it looks like the master's fifo is being written to but never read from.

I have also tried to compile the design libraries and simulate using Nativelink. This produced the same results. My state machines and test bench are written in VHDL. The template IP includes verilog files and to successfully simulate, the simulation language selected at platform designer generation is chosen as verilog. Chosing VHDL produces illegal defparam errors when running the sim. I have added the additional verilog libraries manually for compilation in the 'do' file that may be required (eg altera_ver, lpm_ver). Could the issue be due to the mixed language?

I have been using Quartus 17.1 standard and have tried Questasim versions 10.6b & 10.7a. The third party simulator guide states "The Intel® Quartus® Prime software supports specific EDA simulator versions for RTL and gate-level simulation. QuestaSim*10.6d". Does this mean exclusively this version? I don't have this version number available currently to try.

Any help on simulating the avalon template IP or third party simulation would be greatly appreciated.

Thank you

[Kenny_Tan]

My suggestion is you try on Modelsim_ase version for the simulation first to narrow down whether it is tools issue.

Usually, this would not be a problem as this is a common IP.

https://www.intel.com/content/www/us/en/programmable/documentation/gft1513990268888.html

Questasim support should be 10.6d for Quartus 19.3

Similar to modelsim, Questasim should be 10.5b for Q17.1std version

Can you use the latest release of Quartus instead? It is Q19.1 for std version linux. 18.1 for std version windows.

[CBOLL2]

Thank you for your reply.

I changed to modelsim and tried the versions I had available and is now working.:

Quartus 17.1 standard

Modelsim 10.0e

Many thanks