I am using the video frame buffer II IP in Arria 10 Platform and below is the configuration of the IP.
Input video source (MIPI IP) does not handle the back pressure so I have added a Avalon-ST FIFO which can handle a small back pressure upto FIFO 32 depth.
MIPI IP <---> Avalon-ST FIFO <--> V
As per the Frame Buffer Application Example
Locked Rate Support (No)
Frame Dropping (No)
Frame Repeating (No)
It says "The frame buffer implements a "double buffer", providing very little back pressure to the input, while maintaining the required steady rate at the output. "
I do see the ready output of the Avalon-ST FIFO held low.Hence, there is no new frames being written in DRAM
I believe the Avalon-ST FIFO is not capable to handle the back pressure from video frame buffer IP. However the ready signal from FIFO should not held low all the time. I am adding signal tap to understand this ready behavior from video frame buffer IP.
Only way to recover the system by resetting all modules (MIPI IP, Avalon-ST FIFO and Frame Buffer II IP)
Could you suggest possible configuration or solution to avoid the Avalon-ST Ready held low from FIFO ?
Firstly before I suggest a configuration, based on (MIPI IP <---> Avalon-ST FIFO <--> V):
May I know how is the frame buffer II IP connection? Position of the frame buffer? A simple diagram of your design would help.
In order to use Frame buffer IP ,it is required to follow the Intel® Video and Image Processing (VIP) Suite User Guide. It is not necessary to use Avalon-ST FIFO when using VIP suite, instead the FIFO function is already embedded in VIP suite IP functions. For example in Frame buffer IP, it already have FIFO function embedded in the IP.
For VIP design, it is required to have Clocked Video Input II IP block first in order to convert clocked video formats to Avalon streaming video, before Frame buffer IP block.