FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Avalon Streaming Video VIP

Altera_Forum
Honored Contributor II
‎02-24-2016 03:03 PM
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Hi all, 

I'm working with altera VIP and my question is: 

Is possible for an Altera VIP module to set "start of packet" to '1' the next clock cycle after "end of packet" was '1' (in particular "end of packet" of a data packet)? 

I know that the Avalon streaming protocol would allow this but I want to know if Altera VIP modules can behave like this. 

 

Thanks in advance 

Giusepe
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Altera_Forum
Honored Contributor II
‎02-25-2016 12:08 PM
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Hi, Giusepe 

Yes of course. If source_ready signal is high, consumer able to accept data in the next clock cycle. All others condition doesn't matter
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