05-11-2009 02:24 PM
Well, I get that IP-Module from opencores.org: http://opencores.org/?do=project&who=a_vhdl_can_controllerSo far so good. My problem is, that this IP uses a Wishbone Interface and I need an Avalon Interface. I tried to do convert it with comb. logic(can_top_vhdl.vhd) but it doesnt work. The old top level entity was can_top.v. Can somebody tell me what I am doing wrong? PS: I get a warning in the SOPC-Builder: "byteenable width must be one eighth of data width(8)" I dont have any glue why I get this warning. I got a Nios II CPU with 32 Bits and my byteenable signal is 4 Bits wide.
05-11-2009 07:59 PM
05-12-2009 07:10 AM
from your file can_top_vhdlyour data port is 8 bit wide to avalon, so no need for byteenable. if you add a 4 bit byteenable then your data port is 32bit wide. byteenable is data[31:24] byteenable is data[23:16] byteenableis data[15:8] byteenable is data[7:0] so you have 2 possabilities remove byteenable extend data port
05-12-2009 08:50 AM
Well thx, I found some finished core(avalon) on niosforums.It also doesnt work without byteenable. I just know now, that the wishbone interface is very bad documented.
05-12-2009 09:24 AM
Hi Walther,I also had to connect Altera avalon bus to whisbone! I found this document on Wikipedia (below the link) http://en.wikipedia.org/wiki/wishbone_(computer_bus) (http://en.wikipedia.org/wiki/wishbone_%28computer_bus%29) There is a section named "Comparison", it helped me a lot!