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Altera_Forum
Honored Contributor I
1,154 Views

Avalon - Wishbone Interface

Well, I get that IP-Module from opencores.org: http://opencores.org/?do=project&who=a_vhdl_can_controller 

 

So far so good. My problem is, that this IP uses a Wishbone Interface and I need an Avalon Interface.  

I tried to do convert it with comb. logic(can_top_vhdl.vhd) but it doesnt work. The old top level entity was can_top.v. Can somebody tell me what I am doing wrong? 

 

PS: I get a warning in the SOPC-Builder: 

"byteenable[4] width must be one eighth of data width(8)" I dont have any glue why I get this warning. I got a Nios II CPU with 32 Bits and my byteenable signal is 4 Bits wide.
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Altera_Forum
Honored Contributor I
94 Views

You are better off looking at www.niosforum.com. I believe that there is an avalon version of this core already. If not, there are walk throughs. wishbone and avalon are very similar. 

 

--dalon
Altera_Forum
Honored Contributor I
94 Views

from your file can_top_vhdl 

 

your data port is 8 bit wide to avalon, so no need for byteenable. 

if you add a 4 bit byteenable then your data port is 32bit wide. 

byteenable[3] is data[31:24] 

byteenable[2] is data[23:16] 

byteenable[1]is data[15:8] 

byteenable[0] is data[7:0] 

 

so you have 2 possabilities 

remove byteenable 

extend data port
Altera_Forum
Honored Contributor I
94 Views

Well thx, I found some finished core(avalon) on niosforums. 

It also doesnt work without byteenable. I just know now, that the wishbone interface is very bad documented.
Altera_Forum
Honored Contributor I
94 Views

Hi Walther, 

I also had to connect Altera avalon bus to whisbone! I found this document on Wikipedia (below the link) 

 

http://en.wikipedia.org/wiki/wishbone_(computer_bus) (http://en.wikipedia.org/wiki/wishbone_%28computer_bus%29

 

There is a section named "Comparison", it helped me a lot!
Altera_Forum
Honored Contributor I
94 Views

Thanks for your help. I found some clue now .

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