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Avalon and native interface

Honored Contributor II

Hello Friends, 


I am studying the Altera ddr2 sdram controller. My aim is to develop a logic that shall generate the address and the data (write and read). I am interfacing this logic to the controller,which in turn is interfaced to a memory module outside the chip. I am new to these topics and I have the following querries pls- 


1) The controller data sheet states there are 2 interfaces viz the Avalon and the native. What is the native interface ? 

2) My logic ,in this case is the master and the controller is the slave. Is my supposition correct?  

3) Can you direct me to an example where-in such a connection is done via the Avalon and also the timing diagrams(other than the ones found in the Avalon interface data-sheet,if possible). 



Vinod Karuvat.
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2 Replies
Honored Contributor II

Asking the same question 4 times won't get you more answers. 

If you are connecting your IP to the controller through SOPC builder (which I find more flexible), then yes your IP needs to provide a master interface and the controller is a slave. You could also directly instantiate the controller in your design without SOPC builder and control the slave signals yourself. 

What's wrong with the diagrams on the Avalon specification? 

I think there are some templates for Avalon masters on the forum, you should do a search.
Honored Contributor II

If I remember correctly the native interface interleaves the address and data. The Avalon version presents them concurrently. There could be other differences but that's all I remember. Native is meant mostly for standalone mode and Avalon for SOPC Builder/Qsys. 


Here are some old master templates that you can take a look at that expose the master data outside of SOPC Builder and Qsys: http://www.altera.com/support/examples/nios2/exm-avalon-mm.html?gsa_pos=1&wt.oss_r=1&wt.oss=template... 


Here are some other examples of mastering components which might be overkill for what you are doing but may give you some ideas: 






(note the last link is a Qsys design but the components show work just fine in SOPC Builder).