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Hi,
I am trying to have an Intel IP generate Avalon bus master communicate with my own IP modules. I want these modules to be Avalon-mm slaves.
All the documentation I see on Aavalon bus shows the interconnect done with Platform Designer (QSYS). Is it possible to develop one own's interconnect?
Thanks,
David
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Sure but then you won't be using Platform Designer. You can create custom components that follow the Avalon spec and work in Platform Designer which automatically builds an interconnect for you or you can manually instantiate your custom designs in code, but then the arbitration logic and everything else PD provides is now up to you.
What's your goal here?
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