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Avalon to Wishbone bridge

Altera_Forum
Honored Contributor II
1,065 Views

Hello, 

 

I need to connect a NIOS system to a custom peripheral that uses the wishbone bus standard. I have made some progress, but I am stuck with a weird problem. 

 

But first some background. I am exporting the memory mapped master port from the "Avalon-MM Pipeline Bridge" component in my NIOS system. I am connecting those signals manually in my HDL code. But I need to make the data width 32 bits instead of the default of 16. Which seems easy enough. I just make the data and address widths what I need in Qsys and generate the system. 

 

Unfortunately, when I synthesize the resulting HDL system, weird things start to happen. I should point out that there were no unusual warnings or errors in during synthesis. When I go to Eclipse to regenerate the BSP and run the software, my SystemID register is never non-zero. In fact, the whole NIOS system seems to be dead. And very frequently, the Eclipse editor silently disappears (which I assume means it crashed). I resynthesized the design several times, shut down and restarted all the tools, and restarted the computer. Still the same problem. So then I changed the datapath size back to 16. All the problems went away. 

 

I would really like to use 32 bits for my data path size, but I can't seem to figure out how. Has anyone seen a problem like this before? Is this more a question for Altera support? This issue is very reproducible. 

 

Thanks.
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1 Reply
Altera_Forum
Honored Contributor II
226 Views

 

--- Quote Start ---  

Hello, 

 

I need to connect a NIOS system to a custom peripheral that uses the wishbone bus standard. I have made some progress, but I am stuck with a weird problem. 

 

But first some background. I am exporting the memory mapped master port from the "Avalon-MM Pipeline Bridge" component in my NIOS system. I am connecting those signals manually in my HDL code. But I need to make the data width 32 bits instead of the default of 16. Which seems easy enough. I just make the data and address widths what I need in Qsys and generate the system. 

 

Unfortunately, when I synthesize the resulting HDL system, weird things start to happen. I should point out that there were no unusual warnings or errors in during synthesis. When I go to Eclipse to regenerate the BSP and run the software, my SystemID register is never non-zero. In fact, the whole NIOS system seems to be dead. And very frequently, the Eclipse editor silently disappears (which I assume means it crashed). I resynthesized the design several times, shut down and restarted all the tools, and restarted the computer. Still the same problem. So then I changed the datapath size back to 16. All the problems went away. 

 

I would really like to use 32 bits for my data path size, but I can't seem to figure out how. Has anyone seen a problem like this before? Is this more a question for Altera support? This issue is very reproducible. 

 

Thanks. 

--- Quote End ---  

 

 

- Did you run a simulation? 

- Did the simulation emulate accessing the Wishbone device? 

- Did the simulation work as expected? 

 

If 'yes' to all of the above, 

- Did you input all I/O timing constraints? 

- Did static timing analysis pass? 

 

If 'yes' to all of the above, then maybe consider sending those results to Altera support. If 'no' to any of the above, then you need to do more work. The first suspect in any problem is usually the design element produced by the person who is reporting the error thinking that it must be something else other than what that person created. 

 

You likely haven't posted enough information here for anyone to give you much more detailed advice than this... 

 

Kevin Jennings
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