I have following problem using the <Avalon-to-external-Bus-Bridge>:
I need to build a "PCIe to external Bus-Bridge" using a Cyclone-IV-GX. So I created a System using the Altera PCIe-HIP and connected it to the <Avalon-to-external-Bus-Bridge>.
My external Interface has a data-width of 8Bit and I want to access it using 32Bit data read/writes from CPU.
This is what happens:
If I use only 8Bit read/writes everything is fine and I can access every address of my external interface.
If I use 16Bit read/writes, there is only one 8Bit read/write done with the lowest address on my external interface instead of two.
If I use 32Bit read/writes, there are two 8Bit read/writes done on my external interface instead of four. The first is with the lowest address and the second with the highest address.
For Example if I write 0x11223344 to address 0x00000, the resulting writes on my external bus are 0x44 on address 0x00000 and 0x11 on address 0x00003.
Is there some kind of adapter or converter that can translate 16Bit and 32Bit Avalon Transfers to the corresponding number of 8Bit Transfers?
You may check https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf page 36 for address alignment.
a 32-bit master read from a 16-bit slave results in two read transfers on the slave side. The reads are to consecutive addresses.
To write to specific bytes within a data word, the master must use the byteenable signal. Page 14