Bit slip port in E-TILE transceivers. Native PHY mode

[MUrba10]

Hello,

I have a question regarding bit slip functionality in Stratix 10 E-TILE transceivers, functioning in Native PHY mode. Other Intel FPGA transceivers have a dedicated bit slip port (for example rx_pma_clkslip in Stratix 10 H-Tile transceivers), which allows to instruct deserializer to skip one serial bit to achieve word alignment.

I wasn't able to find similar input in Stratix 10 E-TILE transceivers. How do I achieve similar functionality using E-TILE transceivers? Should I use PMA attribute "Rx Phase Slip" (0x000E)?

Thank you!

[CheePin_C_Intel]

Hi,

As I understand it, you have some inquiries related to the support of bit slip function in the S10 E-Tile XCVR. For your information, there is no support of the bit slip function in the E-Tile XCVR. The RX phase slip feature is for dynamic reconfiguration purpose. You might need to code your bit slip function in core logic if you would require to use it. Sorry for the inconvenience. 

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[MUrba10]

Hello Chee,

Thank you for your answer. Could you please elaborate on what you mean by "The RX phase slip feature is for dynamic reconfiguration purpose."? What happens if I update the value of this attribute?

Best regards,

Mikhail

[CheePin_C_Intel]

Hi,

If you refer to the "Reconfiguring the Duplex PMA Using the Reset Controller in Automatic Mode" section in the E-Tile user guide, you would see RX phase slip is one of the step required. It is used to perform phase offset for the RX recovered clock to suit the new data rate.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin