For my project we need an I2S interface to get audio input. I got some existing VHDL code for an I2S receiver which i can use. I modeling my algorithm in Simulink and then using the HDL coder with Altera Quatras II to synthesize the algorithm. So what i understood by reading the Altera and DSP builder tutorials that i need use a black box to import and convert a VHDL code to Simulink Model. So when i look at the example of the FIR Filter from the DSP builder tutorial, it can import the VHDL files and it creates a block that i can connect to my Simulink blocks with the Input and Output Bus from DSP builder. The problem is i am putting in a Sine Wave with 44.1 kHz, and when i look at the output i get a sine wave of 1 Hz. Can someone explain me why this is happening? Why dont i get a 44.1 kHz signal at the output also? Does it have to do something with the clock?