Bug in HDMI TX IP preventing back-to-back writes to HDMI I2C master

[Talavai]

HDMI IP 23.2-19.7.2, being configured as Source/TX with FRL support, AXI4S video interface (VVP Full), and I2C master, does not accept back-to-back writes to I2C master registers. The attached simulation waveform demonstrates that only one write strobe (Avalon MM write pulse) was passed through the DEMUX to the I2C master, while the external Avalon MM master performed three writes (to SCL_LOW, SCL_HIGH, and SDA_HOLD). Registers read back sequence confirms that only the first register in the write sequence, SCL_LOW, is modified.

 

[Talavai]

Interleaving writes with reads could be used as a workaround for the bug.

[ZH_Intel]

Hi Talavai,

Thank you for reaching out.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZulsyafiqH_Intel

[ZH_Intel]

Hi Talavai,

Thank you for your report.

Based on the discussion with our internal team, we acknowledge your concern on this issue.

We will report it to our internal team to be fix in future release.

Please use the workaround you mentioned to go ahead.

Thank you.

Best Regards,

ZulsyafiqH_Intel

[ZH_Intel]

Hi Talavai,

Good day.

Hope my previous reply was helpful.

Is there anything else I can help you with regards to this case?

If there is no further inquiries, I will transition this thread to community support.

Thank you.

Best Regards,

ZulsyafiqH_Intel

[Talavai]

Hi Zulsyafiq,
Thank you for your reply. Please transition the thread to community support.

--

Talavai

[ZH_Intel]

Hi Talavai,

I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Thank you.

Best Regards,

ZulsyafiqH_Intel