Bug in latest Avalon Streaming Dual Clock FIFO

[AFies]

Hello,

I probably discovered a bug in the st_dc_fifo, latest Version 19.4.0, packet mode. sim sources are generated for VHDL by qsys-generate.

As you can see on the screenshot of modelsim, the input data is applied correctly and w/o ready skips.

On the output side, however, you can see (around the mark) that the last beat of the packet is missing, instead 'X' is output. This happens often during simulation, but only at this point valid is asserted as well, resulting in broken data. The FIFO does not overflow.

Can someone confirm this?

[Ash_R_Intel]

Hi,

This thread seems to be left unanswered for a long time. Do you still need support on this?

[AFies]

This sounds like waiting until customers eventually stop complaining is the standard procedure?

The bug was reported almost a year ago and nothing has changed. It still needs to be addressed and I am definitely not impressed by the way Intel handles such issues.

[Ash_R_Intel]

Hi,

Sorry for the inconvenience. Can you please provide steps or files to reproduce the issue?

Regards

[AFies]

I attached the ip core configuration that was used and still results in this bug.

fwiw, I workarounded it by using a plain DC fifo and emulating valid/ready with full/wrreq/rdreq etc. for now. This works without any other changes, which is another indication that we do have a bug here.

Unfortunately I naturally do not a have a seperate test case for the IP core, the bug happens embedded in a larger unit test which requires our local framework to execute. If there are methods how I can extract the relevant part as a stand-alone test for your analysis, please let me know (ModelSim DE 2021.2 rev 2021.04 linux).

[Ash_R_Intel]

Hello,

I tried opening the .ip file that you had attached in the zip file, but not able to open in Quartus for some reason. However, I too had instantiated the IP and ran the simulation, but did not find any issue.

Attaching the .qar file and the waveform file.

Regards,

[AFies]

I see, another attempt: I included the exact data listing and waveform file for this simulation in the attached zip. Please check if you can view it. The bug occurs almost at the end of the trace.