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Valued Contributor III
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Burst size and burst length Avalon MM bridge

Hi,  

 

I am using the avalon memory mapped bridge to interface the FPGA with an external DDR2 chip.  

The naming conventions are a little confusing to me.  

 

In the DDR2 SDRAM controller uniPHY IP, I see a field - Maximum avalon-MM burst length, whereas in the avalon MM pipeline bridge IP, I see - Maximum burst size. 

My understanding is that they are the same.  

Reason - I looked at the interconnect on qsys, and I see no burst adapter being used. However, this is my understanding and I might be wrong. Can someone confirm this for me? 

 

Thanks,  

VK
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Valued Contributor III
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Yes, they are the same. 

In DDR2, the port name is avl_size which have the same meaning like burst size in Avalon MM pipeline. 

 

(This message was posted on behalf of Intel Corporation)
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