FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

C10 HDMI VIP

JLee25
Novice
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Hi,

I am testing the C10 GX HDMI VIP reference design.

https://fpgacloud.intel.com/devstore/platform/18.0.1/Pro/cyclone-10-gx-hdmi-4kp60-with-video-and-image-processing-pipeline-reference-design/

And I noticed that the frame buffer setting of this project is configured to 512-bit instead of 256-bit.

I suppose 256-bit shall meet the connection requirement.

Why you use 512 instead?

 

BRs,

Johnson

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Deshi_Intel
Moderator
596 Views

HI Johnson,

 

You are right. For 32 bit DQ DDR3, we only need 256 bit width to interact with the frame buffer.

 

The existing design of 512 bits on the frame buffer is to reserved for future expansion plan.

 

Thanks.

 

Regards,

dlim

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JLee25
Novice
596 Views

Hi dlm,

Thank you for the reply.

 

Regards,

Johnson

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Deshi_Intel
Moderator
596 Views

You are welcome !

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