We use the Altera CAN IP and HPS CAN API on the Cyclone V SoC.
Even though we always send the same data length (DLC) on a given CAN ID, it is sometimes sent with an incorrect DLC.
Just for reference one frame/ID is transmitted approximately 3700 times and 11 of these frames have an incorrect DLC (either higher or lower).
We have dedicated threads for RX and TX, with RX as the highest priority and using the lowest mailbox numbers (1-32), and mailbox number 33 as TX. But if I understood it correctly the Altera HPS CAN API uses IF1 for RX and IF2 for TX. Or should there be implemented further thread safety when accessing the CAN registers?
We use redundant CAN busses, so all data is transmitted on CAN0 and then on CAN1.
We use the MOTRX register to verify that the frame is transmitted, before transmitting the same data on CAN1.
If I disable the CAN1 transmission the DLC is correct. But the interfaces should be completely separated, correct?
Are there any constraints on the frequency of transmitting frames? I've increased the transmission rate to about 700 msg/s, which yields a bus load of about 15% (using PCAN Explorer 5).
Is it a known issue? Or has anybody else experienced this?
The CAN is enabled in the device tree using Linux;
I highly suggest you refer here;