CIC strange behaviour. Quartus prime 16.0

[Altera_Forum]

Dear Sirs and Madams, 

i try to test CIC ip core. My parameters are: Input Sampling rate 120MSPS System Clock 120MHz Decimation rate 120 Input Channels 16.  Problem is core does not generate start of packet and end of packet signals(of course i have this signal i code). Also i see result on wrong channel. Can anybody say something about this?

[Altera_Forum]

My advice is to run simulation first of all, rather than using hardware captures. With sim you can follow events from the start while with hardware if a fault occurs anytime it will propagate through and gets hard to debug. There is also possibility of timing errors or fifos/rams getting out of control.