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COMPLETION TIMEOUT CONFIGURATION IN P-TILE AVMM IP FOR PCIE

rkv
Beginner
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I want to configure the completion timeout value of P-tile AVMM IP for PCIe. I didn't see any option to do so in the IP. Can anyone help me out with the issue?

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rkv
Beginner
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Kindly note that we are using Intel P-Tile AVMM IP for PCIe, not Intel P-Tile AVST IP for PCIe.

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Rahul_S_Intel1
Employee
739 Views

Hi,

 Kindly note the completion time out is been disabled in stratix 10 , irrespective of Avalon ST or MM

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rkv
Beginner
734 Views

Could you please make it clear? Does 'disabled' means

1)CTO value can't be changed. If so what's the default CTO value?

2)Completion Timeout won't happen. So the P-Tile IP for PCIe will wait for the response indefinitely

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rkv
Beginner
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we are stuck at this point, kindly reply

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Rahul_S_Intel1
Employee
711 Views

Hi,

CTO value can't be changed. If so what's the default CTO value?

>> I do not have a default value for the completion time out 

2)Completion Timeout won't happen. So the P-Tile IP for PCIe will wait for the response indefinitely

No, Timeout will happen, the time out is implemented in HIP ( Hard Ip)

Only difference from other family of Intel FPGA devices is that , customer cannot change the Time out value ,. The Time out will happen by the default value in HIP.

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