COMPLETION TIMEOUT CONFIGURATION IN P-TILE AVMM IP FOR PCIE

[rkv]

I want to configure the completion timeout value of P-tile AVMM IP for PCIe. I didn't see any option to do so in the IP. Can anyone help me out with the issue?

[Rahul_S_Intel1]

Hi ,

 It may be a known issue. Kindly find the KDB

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/ip/2020/when-using-the-intel--fpga-p-tile-avalon--streaming-ip-for-pci--.html?wapkw=Completion%20timeout%20range

[rkv]

Kindly note that we are using Intel P-Tile AVMM IP for PCIe, not Intel P-Tile AVST IP for PCIe.

[Rahul_S_Intel1]

Hi,

 Kindly note the completion time out is been disabled in stratix 10 , irrespective of Avalon ST or MM

[rkv]

Could you please make it clear? Does 'disabled' means

1)CTO value can't be changed. If so what's the default CTO value?

2)Completion Timeout won't happen. So the P-Tile IP for PCIe will wait for the response indefinitely

[rkv]

we are stuck at this point, kindly reply

[Rahul_S_Intel1]

Hi,

CTO value can't be changed. If so what's the default CTO value?

>> I do not have a default value for the completion time out 

2)Completion Timeout won't happen. So the P-Tile IP for PCIe will wait for the response indefinitely

No, Timeout will happen, the time out is implemented in HIP ( Hard Ip)

Only difference from other family of Intel FPGA devices is that , customer cannot change the Time out value ,. The Time out will happen by the default value in HIP.