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rkv
Beginner
216 Views

COMPLETION TIMEOUT CONFIGURATION IN P-TILE AVMM IP FOR PCIE

I want to configure the completion timeout value of P-tile AVMM IP for PCIe. I didn't see any option to do so in the IP. Can anyone help me out with the issue?

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6 Replies
Rahul_S_Intel1
Employee
207 Views

rkv
Beginner
202 Views

Kindly note that we are using Intel P-Tile AVMM IP for PCIe, not Intel P-Tile AVST IP for PCIe.

Rahul_S_Intel1
Employee
197 Views

Hi,

 Kindly note the completion time out is been disabled in stratix 10 , irrespective of Avalon ST or MM

rkv
Beginner
192 Views

Could you please make it clear? Does 'disabled' means

1)CTO value can't be changed. If so what's the default CTO value?

2)Completion Timeout won't happen. So the P-Tile IP for PCIe will wait for the response indefinitely

rkv
Beginner
178 Views

we are stuck at this point, kindly reply

Rahul_S_Intel1
Employee
169 Views

Hi,

CTO value can't be changed. If so what's the default CTO value?

>> I do not have a default value for the completion time out 

2)Completion Timeout won't happen. So the P-Tile IP for PCIe will wait for the response indefinitely

No, Timeout will happen, the time out is implemented in HIP ( Hard Ip)

Only difference from other family of Intel FPGA devices is that , customer cannot change the Time out value ,. The Time out will happen by the default value in HIP.

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