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Altera_Forum
Honored Contributor I
791 Views

CVI inputs

I'm trying to develop an imaging system with the TR4 development kit. My imaging sensor has an analog output and I'm digitizing it using a 14 bit ADC. The ADC produces serial LVDS data and I'm deserialzing it inside the FPGA., 

 

I'm using DVI monitor for the display and I'm using the Terrasic/Bitec HSMC-DVI card for this purpose. I experimented with some of the VIP suites(namely the Clocked Video Output(CVO) and the Test Pattern Generator(CVO) ) to see if I can control the monitor. The TPG and the CVO work.  

 

However, since the CVO requires in the input data stream to be in the Avalon ST-Video format, I'm using a Clocked Video Input(CVI) to convert the incoming stream from the ADC into the Avalon ST-Video format. The data stream from the CVI then goes into the CVO. Besides, the CVI also generates certain control signals such as Start of Packer(sop), End of Packet(eop) and data valid.  

 

When I use the CVI in conjunction with CVO, it my monitor does not even turn on.  

However, when I use the TGP and the CVO I'm able to see the color pattern on the monitor.  

 

I'm wondering if there is something amiss. Specifically, if the TPG is able to control the CVO whereas the CVI is unable to to so, am I missing some control bits? 

 

I have attached a diagram and seek your inputs. I thank you for your time.
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6 Replies
Altera_Forum
Honored Contributor I
50 Views

 

--- Quote Start ---  

I'm using a Clocked Video Input(CVI) to convert the incoming stream from the ADC into the Avalon ST-Video format.  

--- Quote End ---  

 

CVI is not supposed to have raw pixel data stream at its input. 

 

CVI converts clocked video formats (such as BT656, BT1120, and DVI) to Avalon-ST Video. 

The Clocked Video Input MegaCore function accepts the following clocked video 

formats: 

■ Video with synchronization information embedded in the data (in BT656 or 

BT1120 format) 

■ Video with separate synchronization (H sync, Vsync) signals
Altera_Forum
Honored Contributor I
50 Views

 

--- Quote Start ---  

 

I'm wondering if there is something amiss. 

 

--- Quote End ---  

 

 

Use signaltap to check if the CVI is even emitting any Avalon-ST packets. If it isn't, then the problem would be with your connections to the .vid_ prefixed input signals.
Altera_Forum
Honored Contributor I
50 Views

 

--- Quote Start ---  

CVI is not supposed to have raw pixel data stream at its input. 

 

CVI converts clocked video formats (such as BT656, BT1120, and DVI) to Avalon-ST Video. 

The Clocked Video Input MegaCore function accepts the following clocked video 

formats: 

■ Video with synchronization information embedded in the data (in BT656 or 

BT1120 format) 

■ Video with separate synchronization (H sync, Vsync) signals 

--- Quote End ---  

 

 

Thanks. If that is the case, how do I convert raw data to an Avalon-ST Video format?
Altera_Forum
Honored Contributor I
50 Views

 

--- Quote Start ---  

Thanks. If that is the case, how do I convert raw data to an Avalon-ST Video format? 

--- Quote End ---  

 

Apparenly by writing a custom raw data to an Avalon-ST Video format converting module or a custom raw data to BT656 / BT1120 format converting module.
Altera_Forum
Honored Contributor I
50 Views

While in the end you may find it easiest to do so, you do not need to create your own component. 

 

You can definitely use the Clocked Video Input block as you had originally intended. 

 

The input to the Clocked Video Input does not need to be in a standard format. The cited paragraph is limited to discussing how sync data is communicated. If you are supplying input data in a standard format, then the module has the capability to determine the sync information through inspection of the incoming data stream. If you are not using a standard format, or are using a standard format which the module does not understand, then you need to supply the sync information on separate wires. 

 

You can use arbitrary data such as your 14-bit ADC as long as you supply the external sync, which you appear to already be doing although possibly incorrectly. When using your own format, you would obviously need to configure the Clocked Video Input (and the Clocked Video Output, and any other component you add to the pipeline) with the correct configuration for your data. For example, 14-bits per plane, one plane transmitted in sequence. 

 

Since the Test Pattern Generator can not be configured to output video in this format, simply replacing the TPG with the CVI was not your only change to your system, you would have also had to change the CVO for the different formats, and that might be part of your problem as well. 

 

Per my previous reply, the easiest way to get a clue as to what your problem might be is either simulation or SignalTap. Is the CVI emitting Avalon-ST packets? Is the CVO emitting data and syncs on the DVI? etc. etc. etc.
Altera_Forum
Honored Contributor I
50 Views

Also, don't forget to use signal datavalid. For me, that was the first issue. I made a simple system, with a standard format BT.656 entering in Qsys with CVI and then it would exit with CVO, but I could'nt see anything... I had embedded sync and I produced a datavalid reading EAV and SAV words: nothing. But when I tied datavalid to VCC then it worked! I understood that with embedded sync datavalid is ok if the input is either SAV, EAV, blankings or active video: is this correct? 

 

By the way, now I have another problem. I used a deinterlacer IP between CVI and CVO; I use Bob scanline duplication without buffering and then I set CVO to accept the Avalon-ST as a progressive video. But then I see on my monitor only a few lines drawed and after no real video signal. Any ideas why?
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