Hi, i have 2 fpga with 2 video systems implemented with VIP cores.
The first fpga can output DVI with 1024x768 pixels or 768x576 pixels
these configuration are obtained through the following configuration:
Configurable scaler --> CVO
the CVO core is controlled by a control synchronizer core, when i want to change the format resolution, i change the scaler output and i change the video mode of the CVO throught the control synchronizer.
In the other FPGA, the CVI detects the resolution change and i manage data properly.
When i pass from 1024x768 to 768x576 i have no problem,
when i try to do the inverse, so from 768x576 to 1024x768, the CVI registers see 768x858. From this bad configuration i can return to 768x576.
Where can be the problem?
