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PJoer2
Beginner
158 Views

CVP initialisation for ARRIA10

Hi,

 

we would like to know a **SIMPLE** way to be sure that a newly created core image (after design changes) is still compatible to an older peripheral image residing on the FLASH connected to an ARRIA10 FPGA.

 

To be a bit more specific about our application: We would like to have a peripheral image put on the "FPGA-FLASH" once. After powerup this peripheral is loaded on the FPGA and later we load the Core via PCIe.

If we do an upgrade of our firmware we would ideally not have to touch this peripheral image and hence only do a core update via PCIe. To our understanding and testing this should work

for "internal" firmware changes as long as the IO-ring and e.g. PCIe bar sizes did not change compared to the old peripheral image

 

However, we would like to have a way to ensure that we did not accidentely change the IO ring or bar sizes during firmware update which would make our core image incompatible with the "old" peripheral image on the FLASH.

 

From the CPV user guide for ARRIA10 we see the following solution:

-Use CVP for initial and core configuration. Use Partial reconfiguration for our "internal" firmware updates.

 

However, this is not really an acceptable solution. As we do not plan to reconfigure the FPGA during operation, partial reconfiguration seems to be overkill.

 

From testing we found out that the following works:

-With block based design and revision design flow using Quartus Pro we can (in a save way) create different core images which are compatible with one peripheral. By the way from the user guides it is not clear to us whether this is meant to work **for ARRIA10** or not. Maybe someone can clarify?? Note that this approach even allows to do CVP update (which is from user guides not expected to work for ARRIA10??)

 

However, this design flow is also meant to perform updates during operation (CVP update mode for e.g. Cyclon V) and hence adds additional complexity, which we would like to avoid.

 

From testing we also found that a simple approach works:

-Create peripheral and core image from a certain design state. Put the peripheral on the FLASH for startup. Simply change non IO relevant parts of the firmware (without block based design, without revision design flow, withou using Quartus Pro). Use the new core image with the old peripheral.

 

This would be our ideal solution. However with this approach we can not ensure that the new core fits the old peripheral.

 

We tried to compare peripheral rbf files from old and new design states on binary level and were expecting to have identical binaries. However, this was not the case.

(they were almost identical). Note, that it is not a seeding issue as two subsequent compilations of the same design gave identical results (for core and peripheral rbf files).

 

So after all this BlaBla, here come the actual questions:

 

If the peripheral only contains IO information and no internal logic why are the above peripheral rbf files not identical??

Is there a possibility to make our preferd solution save??

 

Many thanks and kind regards

 

Philipp

 

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3 Replies
JohnT_Intel
Employee
53 Views

Hi,

 

If the peripheral only contains IO information and no internal logic why are the above peripheral rbf files not identical??

We no longer have the CvP revision supported on Arria 10 as CvP update features is not available. So we are not able to preserved the periphery image.

Is there a possibility to make our preferd solution save??

The only solution for Arria 10 is to use Partial Reconfiguration features.

 

Sorry for the inconvenience.

PJoer2
Beginner
53 Views

Hi,

 

thanks for the prompt reply!!

 

Just want to be 100% sure about your answer (since this realy has an impact on our development flow):

So what you are saying is :

  • Although, CvP update (creating core images with the revision/block based design flow) works for our tests onARRIA10, it is not officially supported and might not work with future Quartus versions?
  • Although the simple "ansatz" (simply change the design without touching the IO ring) works, there is no check to guarantee that a core works with the old peripheral for sure?

 

Many thanks again and kind regards!

 

Philipp

JohnT_Intel
Employee
53 Views

Hi,

 

CvP update is not available in Arria 10. It has been replaced with Partial Reconfiguration features.

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