FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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CXL Example Design simulation: long simulation time

RicardoC
Beginner
756 Views

Hi,

The Type 3 simulation for the CXL Example Design, v1.7, takes almost 5 hours to complete. It seems that the transactions happen through the serial interface, including the BFM in the testbench.

Is there a way to bypass the serial interface and connect the BFM to the PIPE (or AIB) of the Soft Wrapper?

Is there a way to skip the link negotiation and initializations of the physical interface?

Thank you,

Ricardo.

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2 Replies
JohnT_Intel
Employee
739 Views

Hi,


Currently there is no way to skip it.


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RicardoC
Beginner
691 Views
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