CXL Type 3 Design Example 1.81 simulation issue

[RicardoC]

Hi,

The version 1.81 of the Design Example of the CXL Type 3, using Quartus 23.1 source files, does not behave as intended. The testbench supposedly issues MemWrites of 1500 cache lines, and reads them back for consistency checking. However, an apparent issue in the encrypted macro `CXL_TB_DO_BBS_BUSY_CHECKS (line 187 of tb/tests/cxl_base_test.sv) causes the testbench to stop the MemWrites at packet 1458, which leads to the failure of execution of the next phase, the MemReads.

As a test, I modified the testbench not to use the failing macro, and that assisted the simulation to finish the MemWrites. However, the following error happened during the first read transaction:

"/quartus/hyb-type3/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_180/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: started at 512100001423fs failed at 512100001423fs
Offending '<Protected>'
Error: "/quartus/hyb-type3/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_180/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: at time 512100001423 fs
>>>> Time=512100.001ns, ASSERT - DCC M2SReq PT illegal asserted
>>>> Op=M2SREQDCD_RSVD31, ReIssue=0, Hit=0, CurrSt=TAGSTATE_I, NxtSt=TAGSTATE_ILLEGAL

As a reference, the 1.7 version of the Design Example using the Quartus 22.4 source code works correctly.

I have attached the simulation log files from the original run, and from the modified one.

Thank you,

Ricardo

[JonWay_C_Intel]

Hi there,

Can you also share the sim logs for 1.7 version of the Design Example using the Quartus 22.4 source code works correctly?

I spoke with the FAE. Can you also attach the modified tb/tests/cxl_base_test.sv, so we can understand how the failing MACRO was disabled?

Thanks.

[RicardoC]

Hi,

Here are the files you requested.

Thank you,

Ricardo

[JonWay_C_Intel]

Hi there,

There is a patch for v1.8 Q23.1 at RDC link here: https://www.intel.com/content/www/us/en/secure/content-details/778346/intel-fpga-cxl-1-1-2-0-design-example-programming-files-for-quartus.html?wapkw=766413

Can you install this patch to Q23.1 --> confirm it has been installed correctly in Quartus version -->  regenerate the Type 3 example design --> run simulation?

Let us know if that resolve your problem. 

If not, please provide:
a) AVERY BFM version 

b) VCS version

c) simulation rundir which should have logfiles, trackers and wave dump as well

Thanks.

[RicardoC]

Hi,

Thank you for the suggestion, but our Quartus 23.1 was updated with patch 0.08 back in May to 23.1.0.115.

a) Avery version: 2.5a

b) VCS: P-2019.06-SP2-6

c) The complete run directory is 53GB large, mostly because of the waveforms and sim databases. I have attached all logs and trackers with the exception of the phy tracker, since it is 230MB large when compressed. Let me know if you need this file, so it can be broken down into smaller chunks and uploaded in multiple posts.

Thank you,

Ricardo

[JonWay_C_Intel]

Can you retry with Avery BFM 2.5a.h3 or versions above it?

[JonWay_C_Intel]

I have sent you a private message

[JonWay_C_Intel]

Hi, have you tried with Avery BFM 2.5a.h3 or versions above it. There is a known issue with Avery BFM v.2.5a. Fixed in v2.5a.h3.

[RicardoC]

Hi,

I tried with Avery BFM 2.5b.h1 and the issue still persists. It also fails with the IP generated by Quartus 23.2, using the new out-of-order support:

UVM_INFO /shared/cxltyp3ddr_tb_23p1_acs.ooo/tb/verif/sequences/cxl_m2s_self_check_seq.svh(263) @ 514134.842ns: uvm_test_top.env0.apci_rc.sequencer@@cxl_m2s_self_check_seq [CXL_REPORT] Waiting for Read transaction 0
"/shared/ip_gen_23_2/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_190/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: started at 514227505231fs failed at 514227505231fs
Offending '<Protected>'
Error: "/shared/ip_gen_23_2/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_190/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: at time 514227505231 fs
>>>> Time=514227.505ns, ASSERT - DCC M2SReq PT illegal asserted
>>>> Op=M2SREQDCD_RSVD31, ReIssue=0, Hit=0, CurrSt=TAGSTATE_I, NxtSt=TAGSTATE_ILLEGAL
"/shared/ip_gen_23_2/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_190/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: started at 514227505231fs failed at 514227505231fs
Offending '<Protected>'
Error: "/shared/ip_gen_23_2/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_190/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: at time 514227505231 fs
>>>> Time=514227.505ns, ASSERT - DCC M2SReq PT illegal asserted
>>>> Op=M2SREQDCD_RSVD31, ReIssue=0, Hit=0, CurrSt=TAGSTATE_I, NxtSt=TAGSTATE_ILLEGAL

Thank you,

Ricardo

[JonWay_C_Intel]

HI, I have sent you a personal message.