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CXL type 3 design example Design Assistant Errors

brian1211
Novice
571 Views

In building the CXL Type 3 example design in Quartus Prime Version 23.1.0 Build 115 03/30/2023 SC Pro Edition I get some CDC errors.  I do not see them with the 22.4 build. 

CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized 1
RES-50001 - Asynchronous Reset Is Not Synchronized 2
RDC-50001 - Reconvergence of Multiple Asynchronous Reset Synchronizers in Different Reset Domains 3
TMC-20025 - Ignored or Overridden Constraints 4
TMC-20026 - Empty Collection Due To Unmatched Filter 5
FLP-40006 - Pipelining Registers That Might Be Recoverable 6
CLK-30032 - Improper Clock Targets 7
LNT-30010 - Nets Driving both Reset and Clock Enable Signals 8

 

brian1211_0-1688674982859.png

 

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JonWay_C_Intel
Employee
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Generating and compiling the example design. Will update you if same observation.

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JonWay_C_Intel
Employee
509 Views

These DRC Checks were enabled late in 22.4 onwards. These errors are expected for 23.1 and expected to be fixed by 23.3.

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brian1211
Novice
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So the build should work fine in a system and shouldn't experience any CDC issues with the given errors correct? 

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JonWay_C_Intel
Employee
475 Views

yes, DRC violations are not impacting the functionality so far.

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JonWay_C_Intel
Employee
426 Views

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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