CXL type 3 design example Design Assistant Errors

[brian1211]

In building the CXL Type 3 example design in Quartus Prime Version 23.1.0 Build 115 03/30/2023 SC Pro Edition I get some CDC errors.  I do not see them with the 22.4 build. 

CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized 1
RES-50001 - Asynchronous Reset Is Not Synchronized 2
RDC-50001 - Reconvergence of Multiple Asynchronous Reset Synchronizers in Different Reset Domains 3
TMC-20025 - Ignored or Overridden Constraints 4
TMC-20026 - Empty Collection Due To Unmatched Filter 5
FLP-40006 - Pipelining Registers That Might Be Recoverable 6
CLK-30032 - Improper Clock Targets 7
LNT-30010 - Nets Driving both Reset and Clock Enable Signals 8

[JonWay_C_Intel]

Generating and compiling the example design. Will update you if same observation.

[JonWay_C_Intel]

These DRC Checks were enabled late in 22.4 onwards. These errors are expected for 23.1 and expected to be fixed by 23.3.

[brian1211]

So the build should work fine in a system and shouldn't experience any CDC issues with the given errors correct? 

[JonWay_C_Intel]

yes, DRC violations are not impacting the functionality so far.

[JonWay_C_Intel]

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