CXL type 3 example design increase to 128GB per channel?

[brian1211]

What needs to change in the  CXL type 3 example design to increase the Memory to 128GB per channel?

I tried changing the emif IP to a DIMM, and updated the scripts to not define ENABLE_DDR_DBI_PINS.  I updated the pinouts.  But I get:

Error(129015): Output port DATA_OUT on atom "ed_top_wrapper_typ3_inst|MC_CHANNEL_INST[0].mc_top|GEN_CHAN_COUNT_EMIF[0].emif_inst|emif|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[2].lane_inst|lane_inst", which is a tennm_io_12_lane primitive, is not legally connected and/or configured
Info(129016): Output port DATA_OUT[8] is disconnected, but the Compiler expects this output port to be connected

Any idea what I am missing?

[brian1211]

Tried to attach a *.qar but it's too big.

[JonWay_C_Intel]

Hi @brian1211 i have sent you an personal message.

[crclayton]

What was the solution here? I am also seeing reports of this error.

[brian1211]

@crclayton I think this error was actually simply a duplicate pin declaration, so same IP IO pin had 2 set_location_assignments to 2 different package pins.    Hope that helps. 

[crclayton]

Thank you!

[nelky]

Hi brian1211,

What is the solution?  

I got the similar error,

Error(129015): Output port DATA_OUT on atom "soc_inst|emif_hps|emif_hps|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[0].lane_inst|lane_inst", which is a tennm_io_12_lane primitive, is not legally connected and/or configured

Hope to hear from you soon.

Regards,