FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

Calculate Maximum with DSP builder

Altera_Forum
Honored Contributor II
1,452 Views

Hi, 

 

I have to calculate the delay between 2 signals so I've done a crosscorrelation. 

After that I have to calculate the index of the maximum for each window, I've done it in Simulink and I'm looking for a way to do it with the DSP builder tools because I will have to program a board obviously. 

 

I've posted the picture of the Simulink scheme. 

 

Do you have some ideas? 

 

This is my idea: 

 

1) Find the 0 values with the differentiator block 

 

2) FInd the value form the ones taken before with the highest "y"value (MAX) 

 

3)Find the index of this value 

 

4) Do this operation for each window of"n" points 

 

I think to have accomplished only to the point one.. :( 

 

 

 

THX 

 

http://img150.imageshack.us/img150/2751/sitovq6.jpg
0 Kudos
7 Replies
Altera_Forum
Honored Contributor II
283 Views

try using a comparator, a delay, and a counter. for each "packet" start the counter and initialize the delay to 0. compare between each value of the packet stream and the value in the delay. use the output of the comparator to be the enable pin for the delay, so you can store the input data if the comparison is true. when the counter runs (and the packet is done) you can read the delay value which should be the maximum. 

 

i will see if i can try that out this afternoon and post a screenshot, my MATLAB machine is busy right now. :(
0 Kudos
Altera_Forum
Honored Contributor II
283 Views

NICE! 

 

I will try it!  

 

Thank you !:)
0 Kudos
Altera_Forum
Honored Contributor II
283 Views

i attached what i came up with. i looked for the maximum of an 8-bit random signal. my "packet size" was 100 samples. the top plot is the random data, the bottom is the maximum value held in the delay. as you can see the maximum is held until the packet is done in which case the maximum is cleared to 0. now that i look at my results the input was signed and i was only looking for maximum (not absolute value) but you get the picture. ;) 

 

note: the thumbnail and zipped file are the same, the zip will just be bigger and look better.
0 Kudos
Altera_Forum
Honored Contributor II
283 Views

Really thx for files and picture. On those days I've tried to apply what you suggest and I've solved the problem. 

 

I post a picture of what I've done. 

 

I usa a window of 256 samples and i calculate also the index of the maximum. 

 

http://img84.imageshack.us/img84/7467/sito2bp6.jpg
0 Kudos
Altera_Forum
Honored Contributor II
283 Views

nice work, thanks for the picture. :)

0 Kudos
Altera_Forum
Honored Contributor II
283 Views

I am a bit unsure what is the requirement of this design. If you just want to  

find the maximum(or minimum) of a given sequence of data then you can do  

that readily in HDL(I rather go simulink path for the really hard stuff). 

 

For example if your signal is "data_in" and it is std_logic_vector(15 downto 0)  

then to get the maximum value: 

 

***************************** 

signal max_pos : signed(15 downto 0); 

------ 

data_in_signed <= signed(data_in); 

------ 

process(reset, clk) 

begin 

if(reset = '1')then 

max_pos <= (others => '0'); 

elsif(rising_edge(clk))then 

if(data_in_signed > max_pos)then 

max_pos <= data_in_signed; 

end if; 

end if; 

end process;  

 

maximum <= std_logic_vector(max_pos); 

******************************** 

 

Similarly for minimum:  

signal max_neg : signed(15 downto 0); 

 

process(reset, clk) 

begin 

if(reset = '1')then 

max_neg <= (others => '0'); 

elsif(rising_edge(clk))then 

if(data_in_signed < max_neg)then 

max_neg <= data_in_signed; 

end if; 

end if; 

end process; 

 

minimum <= std_logic_vector(max_neg); 

 

You can use the reset to clear the value and restart at any point e.g. per packet.
0 Kudos
Altera_Forum
Honored Contributor II
283 Views

HDL is certainly a good solution, but simulating in DSP Builder/Simulink is just so sweet. a lot more fun (and faster) than creating a testbench.

0 Kudos
Reply