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Can Avalon-ST Dual Clock FIFO's fifo depth exceed 32?

Altera_Forum
Honored Contributor II
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accroding to the spec <ug_embedded_ip>P15-4,the descriptions for parameter 'FIFO depth',legal value is ONLY 1~32. 

But when I use Qsys ver 12.0 to add the DC_FIFO component,I can type in '1024' to the parameter 'FIFO depth' of DC_FIFO,without error reminding. 

 

What is it?Can FIFO depth of DC_FIFO exceed 32? 

 

Thanks for any reply. 

 

Regards!
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Altera_Forum
Honored Contributor II
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That's a documentation error. I don't know what the maximum is but I know it is much larger than 32. I've used 1k before so you should be fine with that setting.

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Altera_Forum
Honored Contributor II
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Thank you very much! 

And yesterday when I use Qsys,type in '2000'to FIFO depth,it reminds me that "the FIFO depth has to be a power of 2."I think it may be a error in the doc or I confused it.
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Altera_Forum
Honored Contributor II
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You are better off rounding that up to 2048. The memory blocks in the FPGA which make up the storage element of the FIFO have densities that are a power of two. I have flagged these documentation errors so they should be corrected the next time the document is updated.

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Altera_Forum
Honored Contributor II
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Thank you again~

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