I am reading contradictory information about the support for 256 tags with the PCIe HIP. We are using the HIP with it's ST RX/TX interface (Stratix V and newer), not any of the DMA-MM soft-logic provided by Intel.
According to the documentation, 256 tags can be enabled in the HIP, only if our (soft-logic) "Application Layer" validates the completion tags. This is what we want to use. Is this option available?
What is meant by "validating completion tags"? Does it mean we should verify that the completion tags match with our non-posted requests (such as MRd)? Should we signal an error if not?
The other case is where the HIP validates the completion tags, but that leaves only 32 or 64 tags. What does the HIP do to validate the completion tags?
Feb 2nd 2019
In newer datasheets it is mentioned that Configuration Bypass mode is required for 128 or 256 tags. Why is that? Is it because the 256 tags support must be announced by soft-logic as well, instead of by the HIP?
One question to clearify: You wrote "In Stratix V...256 tags can be used..." and then in the 2nd sentence "Our older Stratix V...only...64 tags". I assume Stratix V can only validate up to 64 tags in its PCIe HIP (more tags must be moved into soft-logic). Newer devices (Arria 10 and Stratix 10) do support 256 tags in HIP?
Currently I am targeting Stratix V GX.
> The "Configuration Bypass mode" is required for 128 or 256 tags in only applicable for Arria 10 and Cyclone 10 devices.
Thanks. Does that also apply for "Stratix V GX" devices?