I am using cyclone V and Quartus 18.1
I am cascading two PLLs. the first one has an input of 20 MHz and outputs of 80 MHz and 75 MHz.
It is direct and integer.
The second one uses the 80 MHz output of the first one as a source and outputs 320 MHz and 25.6 MHz. it is also direct and integer
When I place and route, I get PLL cross checking found inconsistant clock settings
Found this Knowledge base article with similar warning message:
Though the Quartus version is different, you may try the solution provided there.
Please let us know if it works for you.