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5741 Discussions

Cannot Simulate FIR II in VHDL

PDone
Novice
364 Views

I used both Quartus 18.1 and 20.1 to create a FIR II IP in VHDL.  Most of the files created are VHDL, but there is one file, altera_avalon_sc_fifo.v that is Verilog. I am simulating with Active HDL 10.5a Expert Edition VHDL License so I am unable to simulate.

Is there a workaround that I can use that will allow me to Simulate this?

0 Kudos
1 Solution
CheePin_C_Intel
Employee
348 Views

Hi,


Glad to hear that it is working. For your information, the Modelsim Intel FPGA Starter Edition has lower performance than Modelsim Intel FPGA Edition which requires license. You can also use Modelsim SE for better performance. 


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin



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6 Replies
CheePin_C_Intel
Employee
357 Views

Hi,


Just wonder if you have had a chance to try simulating with the Modelsim Intel FPGA Starter Edition which come together with Quartus to see if it works? If yes, this could be a workaround for your to proceed. Thank you.


PDone
Novice
354 Views

I will try that and get back to you.

PDone
Novice
351 Views

It works but it runs very slow.   

CheePin_C_Intel
Employee
349 Views

Hi,


Glad to hear that it is working. For your information, the Modelsim Intel FPGA Starter Edition has lower performance than Modelsim Intel FPGA Edition which requires license. You can also use Modelsim SE for better performance. 


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin



View solution in original post

CheePin_C_Intel
Employee
321 Views

Hi,


I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


PDone
Novice
316 Views

The problem that Intel MUST fix is in the IP. When VHDL models are generated, they must include VHDL modules only, no Verilog sub modules at all so that it can be simulated in a VHDL only environment. Using ModelSim - INTEL FPGA STARTER EDITION, which allows dual language simulation allows me to simulate this part of my design separately but it is to limited for me to do a full chip simulation. It is not worth it for us to purchase an additional Verilog Active-HDL license to simulate this one design.

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