FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6018 Discussions

Changing PCIe EP hint PRESET value for PCIe HIP in Stratix V

Honored Contributor II

I am trying to change the starting PRESET coefficient value .... In the Merged Stratix V Gen3x8 design used for PCISIG compliance, these are selectable via a push button switch. 


They are parameters to altpcie_sv_hip_ast_hwtcl ... how do I see inside that module from a RTL or QSYS view ? 

How do I change the EP PRESET's in general for hip components ? 


Thanks, Bob
0 Kudos
0 Replies