Clock and reset interfacing HDL file and DSP advanced design

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Clock and reset interfacing HDL file and DSP advanced design

976 Views

Hi everyone,

I have a question concerning the inteface between a HDL file imported thanks to the block 'HDL Import' and a design implemented with the DSP advanced blockset.

My question is how should I connect the input ports, clock and reset, of my HDL blackbox in order to have everything working correctly in synchronous?

thanks in advance

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.