FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6421 Discussions

Clock and reset interfacing HDL file and DSP advanced design

Altera_Forum
Honored Contributor II
1,041 Views

Hi everyone, 

 

I have a question concerning the inteface between a HDL file imported thanks to the block 'HDL Import' and a design implemented with the DSP advanced blockset. 

 

My question is how should I connect the input ports, clock and reset, of my HDL blackbox in order to have everything working correctly in synchronous? 

 

thanks in advance
0 Kudos
0 Replies
Reply