Clocked Video Input II Overflow

[JLee25]

Hi,

  I am using the CVI II to receive 4K resolution, Quad pixels in C10 GX.

Overflow handling was turned off in Platform Designer.

When the read back of status register Bit 9 shown overflow.

Sometimes resolution parameter changed from 3840x2160 to 3840x2159 but not always.

My question is will the resolution changed whenever there's over flow in CVI

?

And how CVI II get the resolution, as the value is 2159 instead of 2156 when overflowed...

Thank you!

BRs,

Johnson

[Deshi_Intel · Accepted solution]

HI,

Pls see my comment below :

1. My question is will the resolution changed whenever there's over flow in CVI ?

• Yes. It's possible that resolution will change when overflow happened as the IP will insert END OF PACKET early to cut off the existing video transfer instead of let it to complete and finish.

You can read more about underflow and overflow operation in VIP user guide doc chapter 7.7 (page 64)

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_vip.pdf

In short, I would say that the video transfer can't be trusted anymore if overflow happen as it's hard to tell when the data corruption will happen

• My recommendation to you is perhaps you can consider to add in "FRAME BUFFER II" IP before the connection to CVI IP to add more buffer to avoid overflow issue

Thanks.

Regards,

dlim