Hello together,
I've got a problem to get the clocked video output from the Altera VIP suite running into frame locking mode. I want to synchronzie the video output using the SOF input of the clocked video output component.
My system is as follows:
QSys: Test Pattern Generator -> Clocked Video Output <- external connection -> Clocked Video Input (cvi_a) -> Clocked Video Output (cvo_b) -> SDI II IP Core
cvi_a has SOF outputs for synchronization.
cvi_b has SOF inputs for synchronization.
Both components are connected for synchronization processes outside the QSys.
I set register of cvi_a at 0x00 to 0x0F for activating SOF outputs.
I set register of cvo_b at 0x00 to 0x1F for activation frame locking.
The system is working, in the case, that I see a 1080p30 SDI video at the SDI II IP Core output.
BUT, the system is not SOF locked.
The cvi_a didn't generate a SOF signal.
The cvo_b didn't lock as a result of the missing SOF input. And it doesn't generate SOF outputs itself.
-> Does anyone has an idea, why the system is not frame locking?
-> Doest anyone has experiance in frame locking for the clocked video output?
-> Is there a actual example design available for using frame rate locking?
Thank you all,
Best regards!
