- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Dear all,
I am using Quartus II (Prime 18.1) to write verilog program, hoping to realize coefficient reload of FIR IP core, and the simulation results through ModelSim are correct, and all signals actually entering FIR are correct through signal tap.
However, the actual data from FIR is still the data before parameter overload, that is to say, the FIR Coefficient reload does not play a role in the actual operation.May I ask what causes this?
Thanks in advance,
Regards,
LYW
Link Copied
0 Replies
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page