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Altera_Forum

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08-28-2012
05:15 PM

724 Views

Complex multiplication implementation & FFT

Dear all,

I have first a question regarding the usage of DSP resources, and then a remark regarding the complex multiplication implementation with Altera FFT MegaCore. When you implement an FFT, you have the possibility to choose if you want to implement the complex multiplications using 4 multipliers and 2 adders (conventional representation), or 3 multipliers and 5 adders (canonical representation). I have tested both implementation, with the following FFT parameters :Stratix III FPGA targeted, 2048-point transform length, 18-bit resolution for input and twiddle, streaming implementation. When I look at the DSP resource usage after compilation, I have the following : When using 4 multipliers, the FFT uses 24 DSP 18x18, or 24 DSP 18-elements. Here, everything is ok. When using 3 multipliers, the FFT uses 18 DSP 18x18, or 36 DSP 18-elements. There are less multipliers used, but more DSP elements. In the ALTMULT_COMPLEX documentation, it is written that the canonical representation can be used only under certain condition, and in particular it cannot be used for Stratix III FPGA (and more recent). I think this is the cause. Because if I implement the same FFT on Cyclone III FPGA (where the canonical representation can be used), I obtain the same ratio between the number of DSP elements and the number of multipliers used in both cases.Link Copied

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