Configuration settings for Transceiver Native PHY IP Core when using the USB (3.1) Type C interface

[KRoma6]

Hello,

I am working on the Cyclone 10 GX development board and need access to the USB (3.1) interface that connect to the XCVRs. What are the ideal settings in the Transceiver Native PHY IP Core to implement the USB protocol?  Does a designer need to account of the I2C address?

Thanks 

-Kyle

[Deshi_Intel]

Hi Kyle,

Unfortunately USB protocol is not under Intel FPGA support plan, hence you won't be able to find any preset setting in transceiver NativePHY IP nor I have the knowledge to advise you on it. 

For USB protocol solution support, typically Intel FPGA  leverage 3rd party design house like SLS to provide USB solution support to customer.

• https://www.intel.com/content/www/us/en/programmable/solutions/partners/partner-profile/system-level-solutions--inc-/ip/embedded-usb-3-1-gen-2-device-controller--eusb31sf-.html
• https://www.intel.com/content/www/us/en/programmable/solutions/partners/partner-profile/system-level-solutions--inc-/ip/usb-3-0-3-1-gen-1-device--software-based-enumeration-fifo-interface--usb30sf-.html
• Feel free to engage and check with SLS directly

Nevertheless, this is forum community. Hopefully there is other experience forum user that's familiar with USB design able to advise you better.

Thanks.

Regards,

dlim