Configuring Native PHY IP for QSFP transceiver

[lingxi10]

Hi there,

We are trying to configure a transceiver on a stratix 10 device. The transmitter and receiver are on same board. The 50Mhz global clock goes through an IOPLL IP core to create 100Mhz clock for user logic, input clock of the reset controller for both transmitter and receiver, and the input clock for the reference clock of the receiver. Reference clock of the transmitter is the clock pin on QSPF28 Ports, which is 644.53125Mhz. It goes through fPLL IP core of the transceiver and create 500Mhz output clock as indicated by the Native PHY IP core for transceiver with 1000Mbps datarate. 

Now the simulation is working, and we tested the transmitting side using oscilloscope. It seems that the data from the transmitting side is doing correctly. But on the receiver side, the patterndetect signal never goes high and the parallel data cannot be recevied. Below attached the project. I am wondering if some configurations are wrong or we are missing something? Thanks for the help! 

Update: I also attached the simulation screenshot here. The serial data transmitted from the transmitter core is going directly into the receiver core. There are glitches on the data line though. Not sure if anyone has the same problem? 

[Ash_R_Intel]

Hi,

There are some good recommendations for common transceiver related problems. Please follow this link: https://community.intel.com/t5/FPGA-Wiki/What-steps-can-I-follow-to-ensure-I-don-t-have-transceiver/ta-p/1277330

Regards