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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Configuring Software with the Altera PCIe Compiler Address Translation Page Size

Honored Contributor II



I am writing a host bridge driver for the Altera PCIe Avalon MM Bridge, and implementing the part of the software that translates a PCIe address into a CPU address. We would like to implement the software in a general way so that it might be used with many different hardware designs. Therefore it would be preferable to configure the software with the CPU to PCIe address translation page size that was used to instantiate the PCIe IP, but this information maybe isn’t present in the Altera HAL's system.h, nor in one of the device registers? 


Does anyone know of a mechanism where the software might discover the address translation page size with which the PCIe compiler was configured? 




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